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Altera_Forum
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16 years ago

Reg AN427 Example Design on Quartus 9 WE

I like ur input reg VIP example design: AN427 on cycloneIII EP3C120 I tried to synthesize and create programming file instead of the provided sof file. But the Analysis & Synthesis result repo...
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Altera_Forum
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16 years ago

Ok. I tried creating a similar design with same settings & synthesised after assigning pins. When running Analysis & Synthesis i got warnings:

Warning: Assertion warning: Ignoring parameter INDATA_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone III of altsyncram megafunction cannot use input registers with clear signals

Warning: Assertion warning: Ignoring parameter WRCONTROL_ACLR_A that uses input register with clear signal -- RAM block for device family Cyclone III of altsyncram megafunction cannot use input registers with clear signals

And while running I/O Assignment Analysis, i get errors:

Error: Can't place multiple pins assigned to pin location Pin_F4 (IOPAD_X0_Y65_N21)

Info: Pin BITEC_DVI_IO_OUT_DVI_ISEL is assigned to pin location Pin_F4 (IOPAD_X0_Y65_N21)

Info: Pin ~ALTERA_ASDO_DATA1~ is assigned to pin location Pin_F4 (IOPAD_X0_Y65_N21)

Error: Can't place multiple pins assigned to pin location Pin_E2 (IOPAD_X0_Y61_N14)

Info: Pin BITEC_DVI_IO_OUT_DVI_DAT is assigned to pin location Pin_E2 (IOPAD_X0_Y61_N14)

Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is assigned to pin location Pin_E2 (IOPAD_X0_Y61_N14)

Please help me.