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Altera_Forum
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11 years ago

Reference Clock Input for High-Speed Transceivers in Terasic TR4 Eval Board

I am trying to use the Startix IV FPGA on the TR4 Eval Board from Terasic to receive a 15-bit word at 2.3Gbps. The channels use differential signalling and are source synchronous. Also, I have the tr...
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Altera_Forum
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11 years ago

Hi knjayanth

I believe you can send through other ports but normally for transceiver you would have the CDR or the 3rd party device should come with CDR capabilities. Otherwise it would be very hard.

For the 15 channels, you might need to look into bonded mode. That would ensure the channels to channels are aligned.

This will depends on the device you are interfacing with. Normally it would still required a refclk. Of course in the case it does support CDR it could recovered the clock from the transmitted data.