Receive Transceiver clock recovery problem without loopback

Yes, this is the board I am working with.

>> However, none of the REFCLK signals from the transceivers route via the HSMC connector

What do you mean?

I think that clk2_p/n (figure 2.3 in the manual) is the clock that the design sees as the pair hsmb_clk_in_p2 and hsmb_clk_in_n2, which is then used as a refclk further in the code by the CDR (the code is available on the website too).

What I did now is that I connected clk2_p/n (figure 2.3) from one board into the SMA_clk_p/n of the second board, such that the clk2_p/n of the second board is the same as the one from the first board.

I am not sure if the mux that is pictured would create problems though (like adding a delay to the other clock),

It doesn't work though... with this configuration there is no data sent/received by the second board. Either my connections are not what they should be, or the cables I am using aren't doing the job.