Honored Contributor
Honored Contributor>> Can you test your theory? Can you get the first board to generate a clock that you then use on the second board as the reference clock?
This is going to be my next step. I was going to try this this morning but then I lost my motivation when I thought that there would be noise in the SMA connectors etc... so it was probably not gonna work... Your message is encouraging though! I am using the "SFP HSMC loopback demo" as a basis for the design. My board is a DE4 with Stratix IV, connected to an SFP HSMC daughter card through HSMC. The reference clock to do clock and data recovery is derived from hsmb_clk_in2, which comes from the HSMC interface and seems to be generated directly by the daughter card. From what I read, I think I can force the two daughter cards to be using the same clock by using SMA connectors, now I just need to find two of them that will be long enough and hopefully not broken...
