New ContributorFPGA(Cyclone V) is endpoint, outbound. I could able to write data but couldn't read it back.
I have attached the image below. There I have observed that readdatavalid is always low.
Can anyone suggest what may be the reason for readdatavalid low. Why it is not becoming high?
New ContributorDid calibration complete properly on the memory? What type of memory? I've seen it where the write is still pending and cannot complete since the memory is not available (failed calibration) so the reads get held up. Also note that readdatavalid only occurs when you are reading bursts (I think), and if it's just one read then the waitrequest indicates when read data is valid.
Regular ContributorHi,
Is it possible you are asserting too many addresses to read from? From what I'm seeing the waitrequest signal is high most of the time. When asserted, this signal forces the host to wait until the interconnect is ready to proceed with the transfer. At the start of all transfers, a host initiates the transfer and waits until waitrequest is deasserted. This waitrequest delays the read/write process.
You may find this video helpful: https://www.youtube.com/watch?v=8GAqT3nzHeQ
More information about the signals used and burst transfers here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf
Regards,
Nurina
Regular ContributorHi, do you have any updates?
Nurina
Regular ContributorHi,
We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Regards,
Nurina
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