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saranya's avatar
saranya
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4 years ago

Reason for not getting read data valid.

FPGA(Cyclone V) is endpoint, outbound. I could able to write data but couldn't read it back. I have attached the image below. There I have observed that readdatavalid is always low. Can anyone s...
Macnica_FAE's avatar
Macnica_FAE
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4 years ago

Did calibration complete properly on the memory? What type of memory? I've seen it where the write is still pending and cannot complete since the memory is not available (failed calibration) so the reads get held up. Also note that readdatavalid only occurs when you are reading bursts (I think), and if it's just one read then the waitrequest indicates when read data is valid.