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saranya's avatar
saranya
Icon for New Contributor rankNew Contributor
5 years ago

Reason for not getting read data valid.

FPGA(Cyclone V) is endpoint, outbound. I could able to write data but couldn't read it back. I have attached the image below. There I have observed that readdatavalid is always low. Can anyone s...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Is it possible you are asserting too many addresses to read from? From what I'm seeing the waitrequest signal is high most of the time. When asserted, this signal forces the host to wait until the interconnect is ready to proceed with the transfer. At the start of all transfers, a host initiates the transfer and waits until waitrequest is deasserted. This waitrequest delays the read/write process.


You may find this video helpful: https://www.youtube.com/watch?v=8GAqT3nzHeQ

More information about the signals used and burst transfers here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf


Regards,

Nurina