readyLatency of Arria 10 PCIe Avalon-ST IP

Hi Chenyang,

Thank you for sharing your detailed observations regarding the signal behavior of rx_st_ready and rx_st_valid.

You are right about the current IP settings in which both the RX and TX path has a readyLatency of 3. I observed the same from our Design Example generated from Quartus.

According to the User Guide, when it mentions a ready latency of 3 cycles, it does not mean the readyLatency must be exactly 3 cycles. Instead, it means the readyLatency can be up to 3 cycles. The user's Application Layer should be designed to handle the readyLatency up to the specified number, which is 3 in this IP.

Another way to check your readyLatency is via Quartus Platform Designer.

1. Open the .qsys file.

2. Go to View > Component Instantiation.

3. Locate the Arria 10/Cyclone 10 Hard FPGA PCIe IP.

4. Under Component Instantiation tab > Signals & Interfaces sub-tab > click rx_st signals.

5. You should be able to see the Ready latency value configured.

Arria® 10 and Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683647/18-0/datasheet.html

I apologize again for my late response. I hope this has clarified your questions regarding the readyLatency of this IP.

Please let me know if anything remains unclear.

Thanks.

Best Regards,

Ven