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TSUGI's avatar
TSUGI
Icon for New Contributor rankNew Contributor
2 months ago

Where is High Speed Transceiver Demo Design in FPGA Wiki ?

I can't find these demo design.  - Superlite II V4  - Superlite IV  - Soft PRBS BERT Design  - oversampling design and so on.
Transceiver
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hi,

Sorry for the delay. The following are the archive for Agilex F-Tile designs that I could locate. Can you help to check out. Thank you.

1. Multi-Prbs Generators and Checkers

  •  (28/04/2021) Collection of Multi-Prbs Generators and Verifiers used in various transceiver demo's with different bit widths: 32-bit, 64-bit, 128-bit, and 256-bit. Includes test bench as well.

2. Supporting documentation for the F-tile Demo Designs 

3. Description of all F-tile Demo Designs (Excel file)

4. Library of C-functions for F-tile transceivers using AVMM Interfaces

  • Updated (28/01/2022) 

5. Script with useful procedures for use in the system console with Agilex F-tile

  • New (12/08/2022) 
    • Functions to be used with F-tile PHY-Direct/FEC-Direct designs/F-tile Ethernet Hard IP designs (controlling loopbacks, showing PMA settings, performing EHM, setting Media mode to VSR/Optics etc.). Requires NDME to be enabled. Supports both FGT and FHT.
    • ttk-helper-ftile.tcl (V1.0)

6. Soft PRBS with RSFEC Demo Designs

Intel Agilex® device I-Series PCIe development kit

  • NEW (11/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4 channel 25.78125 Gbps soft PRBS test design with RSFEC (528,514) in 2x100G Aggregate mode using FGT transceivers connected to QSFPDD0 and QSFPDD1
  • Updated (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD1
  • NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 200G Aggregate mode using FGT transceivers connected to QSFPDD's
  • Updated (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FGT transceivers connected to QSFPDD's + dynamically reconfigurable internal noise.

Intel Agilex® device I-Series SI/SOC Board

  • NEW (06/12/2021) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): 2x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD0 and QSFPDD1
  • NEW (06/12/2021) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile device): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD0

Intel Agilex® device I-Series HS Demo Board

7. Soft PRBS Demo Designs (no FEC)

Intel Agilex® device I-Series SI/SOC Board

  • NEW (02/02/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): 2x8x1 channel 53Gbps PAM4 soft PRBS test design using FGT transceivers connected to QSFPDD0 and QSFPDD1

Intel Agilex® device I-Series PCIe development kit

  • Updated (31/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's with dynamically reconfigurable internal noise logic.
  • (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel NRZ 25.78125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's
  • (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's
  • (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 3x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's

Intel Agilex® device I-Series HS Demo Board

  • Updated (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel PAM4 53.125 Gbps soft PRBS test design using FHT transceivers connected to OSFP800
  • Updated (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel PAM4 106 Gbps soft PRBS test design using FHT transceivers connected to OSFP800

8. Superlite II V4 (with/without KR FEC)

9. Superlite IV (RSFEC)

Intel Agilex® device I-Series SI/SOC Board

  • NEW (18/01/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): Superlite IV design using 4 instances (one per F-Tile) of 2 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 8 lanes at 53.125 Gbps to transport 400 Gbps of raw data (transparent transmission of a 1,024-bit bus), total bandwidth = 4x400Gbps = 1.6 Tbps
  • NEW (18/01/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): Superlite IV design using 4 instances (one per F-Tile) of 3 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 12 lanes at 53.125 Gbps to transport 600 Gbps of raw data (transparent transmission of a 1,536-bit bus), total bandwidth = 4x600Gbps = 2.4 Tbps

Intel Agilex® device I-Series PCIe development kit

  • NEW (26/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 4 instances of 1 PHY direct IP configured in 100Gbps with KPFEC, bonded across 2 lanes at 53.125 Gbps to transport 100 Gbps of raw data (transparent transmission of a 256-bit bus), total bandwidth = 4x100Gbps = 400 Gbps.
  • NEW (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 3 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 12 lanes at 53.125 Gbps to transport 600 Gbps of raw data (transparent transmission of a 1,536-bit bus)
  • Updated (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 2 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 8 lanes at 53.125 Gbps to transport 400 Gbps of raw data (transparent transmission of a 1,024-bit bus)

10. 400GbE

11. 100GbE

12. 25GbE

13. 10GbE