TSUGI
New Contributor
New ContributorWhere is High Speed Transceiver Demo Design in FPGA Wiki ?
I can't find these demo design. - Superlite II V4 - Superlite IV - Soft PRBS BERT Design - oversampling design and so on.
Forum Discussion
CheepinC_altera
Regular Contributor
Regular ContributorHi TSUGI,
Sorry for the delay. Seems like there is a glitch with the system recently which is causing issue for me to add new post.
For your information, I managed to locate a few S10 Superlite IV design links after consulting the admin. Would you mind to check if you are able to download them using the following links? Please let me know if there is any concern. Thank you.
6. Superlite IV (using Native PHY) (with FEC)
PAM4
- Updated (27/04/2021) Stratix 10 TX SI Board (Prod) : 1.8Tb Superlite IV Demo design using 18 times 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 1.8Tbits of raw data (+ I2C) (Native PHY + KPFEC)
- (12/02/2019) Stratix 10 TX SI Board (S1) : 100G Superlite IV Demo design using 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 100 Gbps of raw data (Native PHY + KPFEC)
- (17/04/2019) Stratix 10 TX SI Board (S1) : 400G Superlite IV Demo design using 8 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 400 Gbps of raw data (+ I2C & Fan Control + tested with 400G Optics) (Native PHY + KPFEC)
- (13/02/2019) Stratix 10 TX SI Board (S1) : 600G Superlite IV Demo design using 12 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 600 Gbps of raw data (Native PHY + KPFEC)
- (08/03/2019) Stratix 10 TX SI Board (S1) : 1.8Tb Superlite IV Demo design using 3 times 12 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 1.8Tbits of raw data (Native PHY + KPFEC)
NRZ
- (19/02/2019) Stratix 10 TX SI Board (S1) : 600G Superlite IV Demo design using 24 lanes at 25.78125 Gbps with NRZ encoding and RS-FEC to transport 600 Gbps of raw data (Native PHY + KPFEC)
