Forum Discussion

MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

User controlled burst refresh

Hi, I have a problem regarding DDR3 EMIF IP can't bursting user control refresh. I am debugging my EMIF test design on Cyclone 10 GX development board. The situation is that it takes long time to ...
Memory
MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
27 days ago


For my point 4, you said:
>I don't think you need to enable it from the user logic.

Is "it" referring  cfg_user_rfsh_en register?

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
15 days ago

Hi MamaSaru ,

 

"Is "it" referring  cfg_user_rfsh_en register?"

-Yes

 

Maybe you also can try to assert read for one clock cycle only instead of assert read until readdatavalid.

 

 

Regards,

Adzim

  • MamaSaru's avatar
    MamaSaru
    Icon for Occasional Contributor rankOccasional Contributor
    13 days ago

    Adzim,

    For my point 4 and 1, altera should provide correct information to users.

    If the cfg_user_rfsh_en register is not needed to access from user logic as you said,

    altera should revise Page 223, Section 9.4.6.1 up to correct waveform and put its explanation.

    I do not wat to try something and discard it back and forth.

    Does someone from altera can answer my question points?

    Regards,

    Masaru