Regarding MIPI CSI 2 TX

Hi Wincent,

Thanks for your reply,

it is a custom design, I instantiated MIPI CSI 2 and D- PHY IP's, I have made some progress regarding tready signal after couple of changes, but there is not improvement from D-PHY interface side.

U suggested to enable HS clock, but from design, i guess those signals are generated by IP's itself.

Though I have enabled resets, and configured registers for MIPI CSI 2 . 

From data sheet of MIPI DPHY IP, what I have understand is LINKn_Dm_TxRequestHS must be asserted.

" A low-to-high transition on
TxRequestHS can only happen when Stopstate is
asserted. The protocol layer asserts TxRequestHS
for the clock Lane at the same clock cycle or in
previous clock cycles of the TxRequestHS of the
data Lanes."

But is not happening. Correct me if am missing anything.

FYR,

Below is snapshot.

Thanks.