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maagnus0re's avatar
maagnus0re
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8 days ago
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MIPI CSI IP using M20K ram for 128 bits

I'm looking at the design assistant warnings for my project. And I see some weird usage by the mipi csi 2 core (Agilex 5 device, intel_mipi_csi2 v3.0.0). I'm greedy about my ram blocks, and I do not ...
  • Wincent_Altera's avatar
    7 days ago

    Hi maagnus0re ​ ,

    I just try to understand which design are you refer to ? Is it from Design Example ? if yes , which version of Quartus you are using ?

    or this is your custom design of trying to add multiple mipi stream ?
    Can you show me the whole complete log of the design assistant warning ?

    If I understand correctly from your issue description, you are trying to use MLAB instead of M20k provided in MIPI CSI 2 IP, As far as I know the reason of using M20K RAM blocks for deskew FIFOs is because deskew across multiple lanes requires reliable, synchronous FIFO operation, and the IP core is designed to auto-generate these using M20Ks by default—not MLABs. There are no user-facing options or alternative IPs that allow use of MLABs for this function as of now.

    Regards,
    Wincent_Altera