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MK_ABQ
Contributor
ContributorLVDS Output of FPGA
Hi all, I am using Arria 10 FPGA part number: 10AX066N2F40E1HG for one of my projects. There is a clock output from FPGA that goes to an external chip. This clock is configured as LVDS. Currently d...
FvM
Super Contributor
Super ContributorHi,
observing "triangle" (slow rise/fall time) waveform suggests that you are no terminating LVDS outputs correctly. To see expected waveform according to LVDS standard, output need to be terminated with 100 ohm differential respectively 50 ohm single ended. Expect trf of e.g. 0.3 ns with correct termination.
Regards Frank
