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Rleduc's avatar
Rleduc
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2 years ago
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JESD204B IP (RX) - K28 character not recognized

Hello dear community, With Arria 10 SoC-FPGA (Terasic HAN Pilot Plateform), I try to receive data from ADC (AD9250) that sends serialized data on 2 lanes with JESD204B protocol. I properly set ...
  • skbeh's avatar
    2 years ago

    Hi Roman


    It looks like you are facing SYNCN signal not de-aserted issue, hence the K28 character not being recognized.

    You can refer to below Fault Tree Analysis (FTA) of JESD204B SYNCN Signal to determine the possible root causes.


    Fault Tree Analysis (FTA) JESD204B SYNCN Signal Not De-asserted link:

    https://community.intel.com/t5/FPGA-Wiki/FTA-JESD204B-SYNCN-Signal-Not-De-asserted-Issue/ta-p/735963


    This FTA_JESD204B_sync_n_not_de-assert consists of a FTA diagram and table used to debug and root cause the SYNC_N signal not de-asserted issue happens in the JESD204B subsystem. In the FTA diagram, multiple hypothesis are made based on the failure symptom as described. For each of the hypothesis, it can have 2nd level or up to 3rd level suspects.


    Hope this helps.


    Regards

    Soon