New Contributor
New ContributorRong,
Thank you for your suggestions!
I removed the F-Tile for the PCIe endpoint, and the PRESERVE_UNUSED_XCVR_CHANNEL settings. as suggested. The multiple-driver error remains. This error occurs within the <design>_auto_tiles hierarchy, so there is little I can do address this in my design.
Are there any other possilble work-arounds?
Many thanks,
Ed.
ContributorError(13076): The pin "ftile_eth|u0|eth_f_0|sip_inst|rd_ptr_sync|ml[0].lrm.CLK0[0]" has multiple drivers.
>>You need to check this clock. The report says it is driven by multiple sources.
>>You can also generate a 400G example design as a reference to confirm your clock connections.
Regards,
Rong
New ContributorThe multiple clock error is deep inside of a hierarchy generated by Quartus. I have tried many configurations of the F-Tile and its clocking IP, but without success.
As for the 400G example design, while I can generate an example design, Quartus does not support the F-Series Development Kit 2xF-Tile DK-DEV-AGF023F. as a target device. Since I can successfully compile for other devices, I am assuming my configurations are correct.
This is blocking our use of the dual- F-Tile device for ethernet. Are you able to generate a 400G Ethernet for the 2xF-Tile dev kit?
Thanks, Ed.
ContributorYou're right. The generated example design is not directly for your target dev kit thus your problem is likely something wrong when you do the design migration.
For the DK-DEV-AGF023FA, your design should use Bank12C, FGTL12C_RX/TX_Q2/Q3 for the 400G, REFCLK_FGTL12C_Q3_RX_CH6P/N for the clock. Based on these pins, your 400G example design still has compilation error. Is my understanding correct?
Regards,
Rong
