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HBhat2
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5 years ago

Avalon-MM datawidth handling for DDR4 controller with ECC

Hi, I am using Stratix 10 SoC dev kit & working with FPGA-DDR4 (16GB) interface. When I enable the 72 bit data width (64 bit data + 8 bit ECC), the user data width(AV-MM) is 576 bit. My assumption i...
HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

Hi,

I got the reply through mail as below.

"

Hi Hariprasad,

Yes, you can data write & read to DDR4 by ignoring MSB 64 bits (575-512) of data.

Thanks,
Intel Forum Support

"

ref:_00DU0YT3c._5004UsShtn:ref

With regards,

HPB