Forum Discussion

amolkumar's avatar
amolkumar
Icon for Occasional Contributor rankOccasional Contributor
23 hours ago

QVLD pins on QDR-IV when AGILEX 7 EMIF IP does not use QVLD

Team,

We are using the CY7C4122KV13 / CY7C4142KV13 QDR-IV SRAM with the AGILEX  7 AGIB022R31A2I2VB.

The memory has QVLDA[1:0] and QVLDB[1:0] output pins that indicate valid read data.

 NOTE: The AGILEX  7 EMIF IP user guide (UG-20218, Section 7.3.3.5) states that the external memory interface IP does not use the QVLD signal.

 

Could you please advise what we should do with the QVLD pins?

  1. Should they be left unconnected on the board, or connected to FPGA pins?
  2. If connected, should they be assigned in the IP or left as general-purpose I/O (for debug only)?
  3. Is any termination or pull-up/pull-down required on these pins?

 

Please let us know the recommended handling.

Regards

amol

Memory

1 Reply

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 hour ago

    Hi amol,


    QVLD pin is not used in EMIF IP and the avalon has the readdatavalid signal to indicate the data is ready to capture during the read operation.

    This pin can be left floating, no connection required at FPGA and memory side.


    If you still want to use it, I think you may need to place it along with data group.

    But this pin will be a GPIO pin since EMIF IP doesn't use it.


    Regards,

    Adzim