Forum Discussion
amolkumar
Occasional Contributor
Occasional ContributorQVLD pins on QDR-IV when AGILEX 7 EMIF IP does not use QVLD
Team, We are using the CY7C4122KV13 / CY7C4142KV13 QDR-IV SRAM with the AGILEX 7 AGIB022R31A2I2VB. The memory has QVLDA[1:0] and QVLDB[1:0] output pins that indicate valid read data. NOTE: The A...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi amol,
QVLD pin is not used in EMIF IP and the avalon has the readdatavalid signal to indicate the data is ready to capture during the read operation.
This pin can be left floating, no connection required at FPGA and memory side.
If you still want to use it, I think you may need to place it along with data group.
But this pin will be a GPIO pin since EMIF IP doesn't use it.
Regards,
Adzim
