Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Quetions about PCIE Avalon-ST adapator TX FIFO?

I read PCIE User Guide(ug_pci_express[1].pdf) and there are definitions about tx_fifo_rdptr and tx_fifo_wrptr on page 99. From these two signal definition, I kown that the depth of Avalon-ST adapator...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi shsh30. Since I'm no expert, & not sure what might change with different PCIE generation options, how about just monitoring when tx_fifo_wrptr increments when you TX your data in? (look in sim or w/ SignalTap) That should verify whether the width is indeed 64b for your configuration.

I think the fifo is used for all types, but again, looking at when tx_fifo_wrptr increments will confirm it for you (when you tx the different types of packets).

Let me step back a second & ask:

What type of performance requirements do you have?

Or what type of traffic pattern are you concerned about?

I ask because most folks can probably get all the performance needed while ignoring the fifo depth, rd/wr ptrs, and credits.

Hopefully, you'd only need to follow the rules for tx_st_ready backpressure.

-Brian