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Altera_Forum's avatar
Altera_Forum
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13 years ago

Questions about SGDMA's IN connected to Avalon-ST Dual Clock FIFO.

If SGDMA(Stream to Memory)'s IN is connected to Avalon-ST Dual Clock FIFO's out,the there are SOP,EOP signals built in SGDMA IN port. The SOP,EOP inside SGDMA IN port is INPUT attributes,and the D...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I'm sorry I don't understand your question. A packet size of 0x2000 is more than 512 bytes. The SOP and EOP signals just signal the start and end of a packet. When the DC_FIFO receives a packet , its start will be signaled by a SOP high, and its end by a EOP high. The DC_FIFO will just reproduce the same behaviour on it's output, asserting the SGDMA's SOP output at the start of packet and EOP at its end. If you configure the SGDMA to use the EOP signal (i.e. set the transfer length to 0 bytes) then it will read data coming from the DC_FIFO until it sees the EOP signal asserted.