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Altera_Forum's avatar
Altera_Forum
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13 years ago

questions about pcie hip and dma qsys design example

Hi all, I have two questions about the "readaddress" and "writeaddress" registers of dma ip in PCIE Qsys design example. (the design example in PCIE user guide chapter 17) If I want the dma t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

After I study some posts in this forum and the "PCIE-to-AvalonMM address translation table" in PCIE user guide, I find the answers.

Today I start to write a program with Jungo driver in order to test the DMA.

Now I have a new problem - the DMA status is always "busy" if I want to copy data more than 4 bytes from FPGA to PC.

If I set the DMA length register as 4, DMA completes and I can see 4-bytes data.

However, if I try to copy more data (8 bytes or 4096 bytes...), the DMA status register always shows me "busy" and the data in the allocated memories on PC are not changed.

Could anyone please give me some ideas on how the solve this problem?

Thanks.