question of io timing constraints of (r)gmii of the triple speed ethernet mac

hi,

I have a question of io timing constraints of (r)gmii signals of Altera's

triple speed ethernet MAC core. Within the tcl/sdc constraint file generated

by megawizard, I cannot find the setup/hold timing constraints of the (r)gmii

signals. Only the fast input/output register constraints like below

""

set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_d

set_instance_assignment -name FAST_INPUT_REGISTER ON -to gm_rx_dv

# Optimize I/O timing for MII network-side interface

set_instance_assignment -name FAST_INPUT_REGISTER ON -to m_rx_col

...

"

Altera support said it should be ok. But I still doubt if the constraints above

enough for the (r)gmii signals.

Actually I have meet a case before that the design function did not work correctly

because of the timing of the status signals of Altera SPI4 core. The timing violation did

not show up in the classic timing analysis, but reported manually with TimeQuest tools.

Again there is no io timing constaints for SPI4 signal.

does anyone have idea of this?

Thanks,