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Altera_Forum's avatar
Altera_Forum
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16 years ago

Question about the Avalon ST interface from PCIe Hard IP

I have a question about the Avalon ST interface that is coming from the Stratix4GX PCIe hard IP. I do not have enough understanding on this so I am not sure whom to ask about this. This is for the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You mention that you are planning on first storing all the information in FIFO. This means that that the FIFO needs to be deep enough to handle the number of transactions the endpoint can handle in post, non-posted and completion channels. Thus the FIFO may need to be fairly deep. Is that correct?