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Altera_Forum's avatar
Altera_Forum
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16 years ago

Question about the Avalon ST interface from PCIe Hard IP

I have a question about the Avalon ST interface that is coming from the Stratix4GX PCIe hard IP. I do not have enough understanding on this so I am not sure whom to ask about this. This is for the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Since this is a memory write cycle, it is posted cycle. So the tag field does not have any menaing and may be that is why the tag field is 0. As per my understanding any memoy write is posted - regardless of prefetchable or non-prefetchable address range. For my application I may not need I/O write (which is non-posted).

Do you use ready signal to throttle the endpoint while the active command is being processed by the application logic? The design example does not seem to use any throtling mechanism.