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Altera_Forum's avatar
Altera_Forum
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16 years ago

Question about the Avalon ST interface from PCIe Hard IP

I have a question about the Avalon ST interface that is coming from the Stratix4GX PCIe hard IP. I do not have enough understanding on this so I am not sure whom to ask about this. This is for the ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I'm working on a PCIe core design myself right now, so I'll try to help (caveat: my code isn't working yet!).

I don't see a problem with tag being 0x00. It just has to be unique among the transactions going on. I wouldn't be surprised if some implementations used 0x00 as the first tag and just incremented for subsequent transactions.

I believe you have the address correct. Since it is a 64-bit aligned address, the data will be in the following word (Altera aligns it as if you are interfacing to a 64-bit memory internally). If it had been a non-64-bit aligned address (say, 0x0020_0014), it would have packed that first (and only) data word into the second clock.

So, anyway, I think you are on the right track. Good luck!