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Altera_Forum's avatar
Altera_Forum
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15 years ago

question about altmemphy

If the altmemphy is configured as burst length=8, full rate, ddr2 data width=16. Then one read command will trigger the altmemphy to perform a burst 8 read, that is 8*16=128bit data.

but the altmemphy only connect 32 bit ctl_rddata to controller, so how does altmemphy know which 32 bit in the 128 bit data to put on the ctl_rddata bus?

Thanks a lot!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The controller well feed the 128 bits out over 4 clock cycles (32 bits each), known as beats, starting with the lowest address first.