question about ALTLVDS

Please supply more details on your LVDS bus.

1) Are the control board to peripheral connections point-to-point?

If so, and the links are unidirectional, then the protocol is standard LVDS. The Cyclone III device will work fine.

2) If the bus is a multi-drop LVDS (M-LVDS), then you will need to check how things are terminated (on the backplane), and whether the Cyclone III device can drive enough current over the backplane.

LVDS drives 3.5mA into 100-Ohms to create a 350mV signal. M-LVDS terminates the bus at either end of the bus with on the order of 100-Ohms (it might be different if simulations showed it would provide a better termination), so the pair of terminations look like a 50-Ohm load. The 3.5mA then generates only 350mV/2 = 175mV. This might not be enough for the receivers to work (usually it is). If Cyclone III can support M-LVDS (read the data book), then you should be able to boost the LVDS driver output current.

3) If the bus is bidirectional, or LVDS drivers need to be tri-stated, then you might be in trouble with the FPGA. The Stratix II parts cannot disable their LVDS drivers. You will need to check whether the Cyclone III devices have the same (stupid) feature.

National Semiconductor has lots of external transceivers that can be tri-stated, so you can use those attached to regular single-ended I/O pins (depending on I/O rate required for your application).

As for clocking, it depends on timing. If you can change/reconfigure the designs of the control and peripheral board, then you can design the master to launch the signals with the required timing. If the peripherals use a PLL, then you can change the PLL phase to capture data. You can configure the ALTLVDS component with an external PLL, and then use the ALTPLL_RECONFIG component to step the LVDS receiver clock phase. You can use that to perform an eye-sweep of the data, and then adjust the clock to the optimal location.

Cheers,

Dave