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nigelkgordon's avatar
nigelkgordon
Icon for New Contributor rankNew Contributor
2 years ago

Quartus MSGDMA core when used between Memory Mapped and Avalon ST transfers

The Quartus MSGDMA core when used between Memory Mapped and Avalon ST transfers.

I am able to enable packet support with the Channel interface on the Avalon-ST side but how does Channel number get interpreted/generated by the IP core?

If it does nothing then what is the point of the option?


Pcie

9 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi Nigel Gordon,


    Just to let you know that we have receive your case, we will need sometime to investigate into this.


    Thanks


  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    When used as Memory Mapped and Avalon ST transfers, the multi channel settings will be available, it is use to when u also have multi channel Avalon ST to be connected to.


    • NGord's avatar
      NGord
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Yes, but in the ST- Memory Mapped direction, how does the channel bit get translated to Memory Mapped address?
      I assume the Channel bit is just ignored?
      And in the Memory Mapped to ST direction, how does the channel bit get generated or is it just zero?

    • NGord's avatar
      NGord
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      I dont think you are grasping the question.
      Here are two examples:

      (i), for an Avalon -ST to a Memory mapped transfer, if I have one channel bit enabled, which can be set to a 0 or a 1, how does that manifest itself on the Memory mapped interface? Is it ignored?

      For a Memory mapped to Avalon-ST transfer, if I have one channel bit enabled, what causes the channel bit to be set to a 0 or a 1?
      Is it always a 0?

      • ShengN_altera's avatar
        ShengN_altera
        Icon for Super Contributor rankSuper Contributor
        2 years ago

        Hi,

        (i), for an Avalon -ST to a Memory mapped transfer, if I have one channel bit enabled, which can be set to a 0 or a 1, how does that manifest itself on the Memory mapped interface? Is it ignored?

        For MSGDMA with Streaming to Memory-Mapped mode, the channel enabled option will be grey out means can’t be enabled. So I would say that’s right it’ll be ignored.

        For a Memory mapped to Avalon-ST transfer, if I have one channel bit enabled, what causes the channel bit to be set to a 0 or a 1? Is it always a 0?

        For MSGDMA with Memory-Mapped to Streaming mode, if channel enabled with channel width of 1 means ya the channel width bit will be 0 check this link https://www.intel.com/content/www/us/en/docs/programmable/683130/23-3/component-configuration-1-register.html so the number of channel is 1 channel which is CHANNEL_WIDTH + 1

        Thanks,

        Regards,

        Sheng

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



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