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nigelkgordon's avatar
nigelkgordon
Icon for New Contributor rankNew Contributor
2 years ago

Quartus MSGDMA core when used between Memory Mapped and Avalon ST transfers

The Quartus MSGDMA core when used between Memory Mapped and Avalon ST transfers. I am able to enable packet support with the Channel interface on the Avalon-ST side but how does Channel number get...
Pcie
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


When used as Memory Mapped and Avalon ST transfers, the multi channel settings will be available, it is use to when u also have multi channel Avalon ST to be connected to.


  • NGord's avatar
    NGord
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Yes, but in the ST- Memory Mapped direction, how does the channel bit get translated to Memory Mapped address?
    I assume the Channel bit is just ignored?
    And in the Memory Mapped to ST direction, how does the channel bit get generated or is it just zero?