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nigelkgordon's avatar
nigelkgordon
Icon for New Contributor rankNew Contributor
2 years ago

Quartus MSGDMA core when used between Memory Mapped and Avalon ST transfers

The Quartus MSGDMA core when used between Memory Mapped and Avalon ST transfers. I am able to enable packet support with the Channel interface on the Avalon-ST side but how does Channel number get...
Pcie
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


When they are not enabled, the channel bits are 0.


  • NGord's avatar
    NGord
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    I dont think you are grasping the question.
    Here are two examples:

    (i), for an Avalon -ST to a Memory mapped transfer, if I have one channel bit enabled, which can be set to a 0 or a 1, how does that manifest itself on the Memory mapped interface? Is it ignored?

    For a Memory mapped to Avalon-ST transfer, if I have one channel bit enabled, what causes the channel bit to be set to a 0 or a 1?
    Is it always a 0?

    • ShengN_altera's avatar
      ShengN_altera
      Icon for Super Contributor rankSuper Contributor
      2 years ago

      Hi,

      (i), for an Avalon -ST to a Memory mapped transfer, if I have one channel bit enabled, which can be set to a 0 or a 1, how does that manifest itself on the Memory mapped interface? Is it ignored?

      For MSGDMA with Streaming to Memory-Mapped mode, the channel enabled option will be grey out means can’t be enabled. So I would say that’s right it’ll be ignored.

      For a Memory mapped to Avalon-ST transfer, if I have one channel bit enabled, what causes the channel bit to be set to a 0 or a 1? Is it always a 0?

      For MSGDMA with Memory-Mapped to Streaming mode, if channel enabled with channel width of 1 means ya the channel width bit will be 0 check this link https://www.intel.com/content/www/us/en/docs/programmable/683130/23-3/component-configuration-1-register.html so the number of channel is 1 channel which is CHANNEL_WIDTH + 1

      Thanks,

      Regards,

      Sheng

      • NGord's avatar
        NGord
        Icon for Occasional Contributor rankOccasional Contributor
        2 years ago

        OK,

        For Avalon -ST to a Memory mapped transfer, I am satisfied the Channel bits have no affect since the Channel Enable bit is greyed out.

        For Memory mapped to a Avalon-ST transfer, I am going to assume that the Channel bit(s) , when enabled, are always zero.