New Contributor
Occasional ContributorI dont think you are grasping the question.
Here are two examples:
(i), for an Avalon -ST to a Memory mapped transfer, if I have one channel bit enabled, which can be set to a 0 or a 1, how does that manifest itself on the Memory mapped interface? Is it ignored?
For a Memory mapped to Avalon-ST transfer, if I have one channel bit enabled, what causes the channel bit to be set to a 0 or a 1?
Is it always a 0?
Super ContributorHi,
(i), for an Avalon -ST to a Memory mapped transfer, if I have one channel bit enabled, which can be set to a 0 or a 1, how does that manifest itself on the Memory mapped interface? Is it ignored?
For MSGDMA with Streaming to Memory-Mapped mode, the channel enabled option will be grey out means can’t be enabled. So I would say that’s right it’ll be ignored.
For a Memory mapped to Avalon-ST transfer, if I have one channel bit enabled, what causes the channel bit to be set to a 0 or a 1? Is it always a 0?
For MSGDMA with Memory-Mapped to Streaming mode, if channel enabled with channel width of 1 means ya the channel width bit will be 0 check this link https://www.intel.com/content/www/us/en/docs/programmable/683130/23-3/component-configuration-1-register.html so the number of channel is 1 channel which is CHANNEL_WIDTH + 1
Thanks,
Regards,
Sheng
Occasional ContributorOK,
For Avalon -ST to a Memory mapped transfer, I am satisfied the Channel bits have no affect since the Channel Enable bit is greyed out.
For Memory mapped to a Avalon-ST transfer, I am going to assume that the Channel bit(s) , when enabled, are always zero.
