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Altera_Forum
Honored Contributor
Honored ContributorQuartus II v10 DDR3 timing problem
Hello I have problems compiling an unofficial reference project for the Arria II GX FPGA Development Kit (http: // www .altera.com/products/devkits/altera/kit-aiigx-pcie.html). The project...
Altera_ForumHonored Contributor
Honored ContributorI have also -
warning massage: Read resync (all conditions) critical warning: DDR timing requierement not met If any one can help?
