quartus 19.4 can not use more than 2 clocked video output II IP at one project?

hi,thank your reply;also,i make some more tests.

1、i just make a project with only one cvo ip(no matter embedded mode or separate mode),all is well;

2、i first add one cvo ip with embedded mode,then add another cvo ip with separate mode, the project can compile but have warring (13410): Pin "vout_hdmi_clocked_video_vid_datavalid[0]" is stuck at GND. With siganl tap ii file,all the cvo (separate) signals are low.

3、i first add one cvo ip with separate mode,then add another cvo ip with embedded mode,the project can not compile with error "Error(13305): Verilog HDL error at vout_sdi_alt_vip_cl_cvo_191_6gvqwty.v(661): can't find port "sdi_cvo_rden" .