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LZhi01's avatar
LZhi01
Icon for New Contributor rankNew Contributor
5 years ago

quartus 19.4 can not use more than 2 clocked video output II IP at one project?

hello,when i use 2 clocked video output II IP,one is separate mode for HDMI interface,one is embedded mode for SDI interface,but the project can not compiled successfull. The quartus(version 194) r...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Thanks for sharing the error screen shot. So, we are dealing with synthesis compilation design error here.

The error message looks like is complaining about design syntax error that's likely induced by user error

  • I presume you are generating 2 separate VCO IP that have different setting insides.
  • Also, my advice to you is pls check to ensure you enabled sdi_cvo_rden port correctly as shown in (page 79, table 31) and also connect the port correctly as shown in (page 29, figure 14) ?
  • Else if you can share your design archived QAR file with me then I can help to review your design connection.

Thanks.

Regards,

dlim