New Contributor
New ContributorFor anyone that comes across this post, the issue with two identical LVDS Receivers sythesizing with different data pipe delays has not yet been resolved. We will be getting boards back next month and I hope I can manually add a pipeline delay to the lower latency Rx pipeline to re-synchronize the data as I was able to do in gate level RTL. It is also worth noting that the exact same code ported to a Cyclone 10LP does not exhibit the same issue at gate level RTL.
The LVDS Transmitter with a PLL shared with the upstream receiver sythesizing away despite functioning RTL was resolved. The Tx input clock was inadvertently assigned to be from a tri-stateable output node instead of the net associated with the input side of that same output buffer. The synthesizer/fitter didn't throw any useful warnings about why the outputs were stuck at ground and only warned that the clock node in question was being converted to an OR gate.
There has been no feedback on why the newer style LVDS transmitter IP core does not include a valid Tx clock generated by the same DDR logic used to run the serdes when the external PLL option is selected. This is especially problematic for odd serialization factors (7 for example) which make generating the non-50% duty Tx clock difficult without knowledge of how many half serialized clock edges the data gets aligned to.
New ContributorA year later... it is worth mentioning that I never did get the Altera LVDS serdes cores to work. They are DDR based for Max10 devices because the clock tree only supports 400MHz. I don't think it was fully polished at the time Intel acquired Altera and they never went back to clean up the bugs. The valid "bit-slip" settings would compile differently even with small code changes and one of my two almost always didn't match RTL sims. Intel FAE support mentioned that one must send a training sequence every time the cores start in order to set the bit-slip values. That doesn't work if you don't have control over the transmitted serial stream. Eventually I abandoned the Intel LVDS cores (both Rx and Tx) and wrote my own which automatically align themselves to a desired word boundary which is completely deterministic relative to the 57% duty cycle clock on a standard "channel link" with 7:1 serialization per channel. Initially I had some timing issues but eventually set the Rx PLLs to be source synchronous instead of the default and suddenly I had all kinds of timing margin for input data capture.
