Quartus 18.1 Soft LVDS transmitter w/ ext PLL core missing tx_outclock ddio generator logic?

Figure2 of this document: https://www.intel.com/content/www/us/en/programmable/documentation/sam1394433606063.html#sam1394435487348 seems pretty clear that using a "shared" PLL to run both an LVDS_receiver and LVDS_transmitter when the reference input clock is "rx_inclock" is supposed to work. So I ask again, how do I get decent support to resolve why this very configuration is not working post synthesis but it works fine in pre-synthesis RTL? Please note that the simulation model is not exactly the same as the synthesized model, things like PLL lock time have to be assumed for simulation, but is still supposed to represent correct logic/pipeline behavior. The synthesized result of attempting to use Rx/Tx shared PLLs or parallel Rx instances with separate external PLLs has resulted in different behavior vs. pre-synthesis RTL.

The final part of this puzzle... if use of separate PLLs results in an added pipeline delay on one of the two 4:28 receivers, why does the Rx output stay syncronized in post-synthesis when the output of a single externally instantiated PLL is connected to both receivers? However, this is exactly the case for which I cannot guarantee input timing at the DDR based serialized clock reference or I would just use this as the final solution.