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I've been told that it something that need to be fixed, but at the moment PCIe is only in verilog so if you've this in Qsys you can generate TestBenches only in verilog.
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I wouldn't be naive. In another thread (
http://www.alteraforum.com/forum/showthread.php?t=30879 (
http://www.alteraforum.com/forum/showthread.php?t=30879)) BadOmen said Altera is using
only Verilog and SystemVerilog for their IP (and examples).
An extract from the MegaCore IP Release Notes and Errata shows it all:
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vhdl example driver fails in simulation The VHDL example driver for designs using the high-performance controller (HPC) fails to simulate.
affected configurations This issue affects all ALTMEMPHY-based designs using the high-performance controller, and targeting VHDL.
design impact The VHDL example driver fails to compile in VCS/VCSMX and hence cannot simulate.
workaround The workaround for this issue is to use the Verilog example driver.
solution status this issue will not be fixed. --- Quote End ---
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