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Altera_Forum
Honored Contributor
Honored ContributorQsys won't generate testbench with VHDL 'application' source...
As described here.... http://www.alteraforum.com/forum/showthread.php?t=31416 .. I have a system that I'm trying to get working with the CycloneIV hard PCIe interface. This is a syste...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- From what I understand you're saying Josyb is correct --- Quote End --- I've been told that it something that need to be fixed, but at the moment PCIe is only in verilog so if you've this in Qsys you can generate TestBenches only in verilog.
