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I have access to a mixed language simulator, I don't give a toss what the
PCIe models are written in, I'm sure I can even hack a verilog tesbench to drive the interface.
I don't even care if there's a verilog wrapper but I _need_ to be able to use my VHDL in a testbench (it's a big design, months of work that I'm _trying_ to transfer from a PCI based interface to PCIe).
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I haven't tried using Qsys for mixed language designs, but I have done this under SOPC Builder. I wanted to use the Avalon-MM BFMs, which are only supplied in SystemVerilog, and only useable from SystemVerilog.
The SystemVerilog testbench that is generated under SOPC Builder is pretty brain-dead; just a clock and reset generator and dangling connections.
So I don't even bother clicking the 'generate simulation' check box inside SOPC Builder, I just take the generated files and create my own testbench.
The tricky thing sometimes is to figure out which HDL files are needed for simulation. For that, I just create a very small test design, and I do check the 'generate simulation' and I then look at the 'include statements in the generated files, and the setup_sim.do file.
I then add my VHDL components to the simulation script, and Modelsim is happy to simulate the whole system.
Perhaps that would be a solution for you too.
Cheers,
Dave
Honored Contributor
