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Hi, yes I saw the same things on Stratix IV.
The problem is the PCIE macro that at the moment has not the code in vhdl.
The only solution is to generate the simulation in verilog (so if you've some custom components in qsys written in vhdl, you've to translate it in verilog for the simulation porpouse).
Note that you can add more sources as component files.
For example you could add a .vhd files used for synthesys and simulation and a verilog file used only in the simulation.
Doing this, when you later compile your project in quartus you use your vhdl file, whereas when in Qsys you generate the simulation files it chose the correct file depending on the setting of the simulation (verilog or vhdl).
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From what I understand you're saying Josyb is correct, this is madness.
I have access to a mixed language simulator, I don't give a toss what the
PCIe models are written in, I'm sure I can even hack a verilog tesbench to drive the interface.
I don't even care if there's a verilog wrapper but I _need_ to be able to use my VHDL in a testbench (it's a big design, months of work that I'm _trying_ to transfer from a PCI based interface to PCIe).
Nial
Honored Contributor
