Qsys won't generate testbench with VHDL 'application' source...

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The only solution is to generate the simulation in verilog (so if you've some custom components in qsys written in vhdl, you've to translate it in verilog for the simulation porpouse).

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It can not be the case that if we prefer to write VHDL code, that we have to manually code the same functionality in verilog, just to be able to simulate a Qsys system?