Qsys won't generate testbench with VHDL 'application' source...

Hi, yes I saw the same things on Stratix IV.

The problem is the PCIE macro that at the moment has not the code in vhdl.

The only solution is to generate the simulation in verilog (so if you've some custom components in qsys written in vhdl, you've to translate it in verilog for the simulation porpouse).

Note that you can add more sources as component files.

For example you could add a .vhd files used for synthesys and simulation and a verilog file used only in the simulation.

Doing this, when you later compile your project in quartus you use your vhdl file, whereas when in Qsys you generate the simulation files it chose the correct file depending on the setting of the simulation (verilog or vhdl).