Qsys pcie ref design - read and write descriptors

Dual read and write FIFOs are only used when the descriptor block is setup for MM to MM transfers. They are needed so that the read and write portions of the descriptor are buffered independently so that the read and write master can operate independently (i.e. the write master doesn't block the read master).

If you want to implement a read or write only mSGDMA you need to switch the dispatcher over to MM-->ST or ST-->MM and only connect one of the master blocks to the dispatcher. So if you wanted to do something like read data over PCIe from the host's main memory then pump the data into some sort of data streaming block you would configure the mSGDMA for MM--ST and not bother writing the write_address value in the descriptor since there is no destination address in that example. I'm not sure how you would modiy the PCIe reference design host code to do this but it should be fairly straight forward if you look at the Nios II driver that is bundled with the dispatcher block.