Qsys PCIe core fails timing

Ok Thanks Dave,

I understand ... believe it or not, after some thought experiment on the weekend ... I figured I would force "Single DW completer" for the PCIe Hard IP and now my test to park on a IMEM location and write and read back patterns immediately works even after NIOS is running. See image below . This tells me that the PCIe Hard IP master may have been doing something wierd. And the NIOS II running maybe changed the state of how the Avalon MM interconnect was behaving such that the PCIe Avalon MM master , BAR1, was getting stale data back on reads.

I may still try simulating with the "Single DW completer" not checked to see what the BAR1 master is doing.

I am interested in your note about the PCIe simulation support. I have dug into the sample testbench that is generated...

The RC memory write/read/compare test needs to be made more general since the BFM assembles a Write transaction, writes the address to that location ... I would like a more general call that writes data as a parameter to a random address.

So, I will move on and next need to commit NIOS II SW to FLASH which is where I had problems previously.

Then CVP and NIOS II SW load via the PCIe link.

Best Regards, Bob.