Qsys PCIe core fails timing

Ok Dave ..

Yes I am going to run Simulation, but it is difficult to get the NIOS II stimulation ... since as I understand that , it is just a BFM master ..

I am thinking that if I can demonstrate using Eclipse, just one NIOS II instrunction being executed under the debugger will cause the conditions

to fail, then I may have information that the JTAG debug port is doing something ie enabling the NIOS II data / instruction masters.

On SignalTap, that will yield more exact information... I will be able to then say the problem is on the PCIe Hard IP side or on the Avalon

MM interconnect fabric. I am currently constraining the PCIe BAR Avalon MM master to be "single DW completer" to see if that will constrain

things to issue a single write / read at a time.

I am still not sure how to run SignalTap and Eclipse at the same time since Eclipse is using the JTAG / USB port that SignalTap would use.

It seems like I would need to commit the NIOS II SW + bootloader to Flash so Quartus would be in control of the JTAG

Ok on PowerP ... I was in PowerPC land for some time.