Qsys PCIe core fails timing

Hi Bob,

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I have a situation where I get stale data back to the RC from the ArriaV or Cyclone IV endpoints ... Has to be a logical issue rather than FPGA or Timing.

I write to a constant location and read back the same location then compare ... then move on to a new write pattern.

It passes until I start the NIOS , even if I just perform a single printf and return.

After that I get stale data ... ie the data from the previous iteration of the test ... where the data I get is the data that was written say 8 writes back , sometime more , sometimes less but a constant.

I am trying to see in Simulation and setting "Single DW completer" on.

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My first question would be can you reproduce this in simulation; I guess "I am trying to see ... " means you have not yet reproduced it. How about SignalTap II tracing of the o

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Seen anything like this before ?

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I did not end up using the PCIe core due to its lack of BFMs. This may be different now, but Altera removed the BFMs from Quartus and did not provide any support for PCIe debug/verification, so I changed my design to use a processor with a PCIe end-point (a PowerPC).

Cheers,

Dave