Qsys PCIe core fails timing

Dave,

I have a situation where I get stale data back to the RC from the ArriaV or Cyclone IV endpoints ... Has to be a logical issue rather than FPGA or Timing.

I write to a constant location and read back the same location then compare ... then move on to a new write pattern.

It passes until I start the NIOS , even if I just perform a single printf and return.

After that I get stale data ... ie the data from the previous iteration of the test ... where the data I get is the data that was written say 8 writes back , sometime more , sometimes less but a constant.

I am trying to see in Simulation and setting "Singel DW completer" on.

Seen anything like this before ?

Thanks, Bob.