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Apparently the `default_nettype setting is preserved across compilation of different verilog sources, and thus the result depends on the order of compilation. I prefer to enable `default_nettype none, to avoid hard to find bugs caused by typos in net names.
It seems sufficient to place `default_nettype wire at the end of each file where I change this setting - now the design compiles.
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This is one reason I like to script the final design. If there are compilation ordering issues, it helps to 'encode' those requirements in the script.
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As for your problems with timing, I am using only Arria II GX and I used to have some timing errors. For me it was sufficient to precisely specify all clocks, enable all optimizations for timing, and add these entries in the top-level .sdc file:
derive_clock_uncertainty
derive_pll_clocks
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Yep, I have all this, and TimeQuest shows the design is fully constrained.
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In 11.1 it was also necessary to add this:
set_clock_groups -asynchronous -group [get_clocks {alt_cal_edge_detect_clk}]
In 11.1sp2, no clock is matched for that setting, so I suppose it is not needed anymore.
I must run some further tests to check if the design works stably, though.
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I get the timing errors under 11.1sp2 as well, so its probably not this. However, I'll take a look at the clocks and see.
Thanks for the pointer.
Cheers,
Dave
Honored Contributor
