Propagation Delays for DSP Builder primitives?

Hello!

How can one fine the Propagation Delays for DSP Builder primitives?

How could the simulation in Modelsim-Altera be done in 'post-place and route' mode? while using "TestBench" block from DSP Builder blockset.

In my design even I use primitives (like simple/complex multipliers and adders, divider, etc ) with 0 pipeline stage, still ModelSim shows 12 clock cycle for results to become stable.

If I use this design with constant inputs it produces correct results (not sure but may be with 12 cycle delay of default clock). How can it be fitted within a system running at certain clock frequency?

Thank you!

Best regards-